ORT8850L-3BMN680C

ORT8850L-3BMN680C FPGAs Overview

Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Programmable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with highspeed serial backplane data transfer. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORT8850L-3BMN680C is made up of backplane transceivers (SERDES) containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-independent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for HDLC for Internet Protocol (IP), designers can build a configurable interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge using our PCI soft core.

The ORT8850L-3BMN680C device offers a clockless High-Speed Interface for inter-device communication on a board or across a backplane. The built-in clock recovery of the ORT8850L-3BMN680C allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scrambling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required.

The Lattice Programmable Logic ICs series ORT8850L-3BMN680C is FPGA - Field Programmable Gate Array 4992 LUT 278 I/O, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

Embedded Core Features

• Implemented in an ORCA Series 4 FPGA.

• Allows a wide range of high-speed backplane applications, including SONET transport and termination.
• No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz—106 MHz clock, and a frame pulse.
• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
• Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex).
• HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are supported.
• LVDS I/Os compliant with EIA-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes.
• Low-power 1.5 V HSI core.
• Low-power LVDS buffers.
• Programmable STS-3, and STS-12 framing.
• Independent STS-3, and STS-12 data streams per quad channels.
• 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic.
• On-chip, Phase-Lock Loop (PLL) clock meets (type B) jitter tolerance specification of ITU-T recommendation G.958.
• Powerdown option of HSI receiver on a per-channel basis.
• HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
• Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates.
• In-band management and configuration through transport overhead extraction/insertion.
• Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted.
• Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
• Built-in boundry scan (IEEE 1149.1 JTAG).
• FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both SONET scrambling. Optional ability to bypass alignment FIFOs.
• 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection
switching applications. STS-192 and above rates are supported through multiple devices.
• ORCA FPGA soft intellectual property core support for a variety of applications.
• Programmable Synchronous Transport Module (STM) pointer mover bypass mode.
• Programmable STM framer bypass mode.
• Programmable Clock and Data Recovery (CDR) bypass mode (clocked LVDS High-Speed Interface).
• Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channelswith redundancy on a single device.
FPGA Features
• High-performance platform design:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 600K FPGA system gates (ORT8850H).
– Meets multiple I/O interface standards.
– 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
• Traditional I/O selections:
– LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input flip-flop/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path.
• New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, LVPECL.
– LVDS include optional on-chip termination resistor per I/O and on-chip reference generation.
• New capability to (de)multiplex I/O signals:
– New Double-Data Rate (DDR) on both input and output at rates up to 350 MHz (700 Mbits/s effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
• Enhanced twin-quad Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations.
– New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects.
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX, and ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing, which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efficient performance.
• SLIC provides eight 3-State Buffers, up to 10-bit decoder, and PAL-like AND-OR-INVERT (AOI) in each programmable logic cell.
• Improved built-in clock management with dual-output Programmable Phase-Locked Loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible.