Manufacturer | INTEL/ALTERA |
Mounting Type | Surface Mount |
Number of I/O | 164 |
Package / Case | 208-BFQFP |
Product Status | Active |
Number of Gates | 5000 |
Programmable Type | In System Programmable |
Number of Macrocells | 256 |
Delay Time tpd(1) Max | 7.5 ns |
Operating Temperature | 0°C ~ 70°C (TA) |
Supplier Device Package | 208-PQFP (28x28) |
Voltage Supply - Internal | 3V ~ 3.6V |
Number of Logic Elements/Blocks | 16 |
The EPM7256AQC208-7 (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM based EPM7256AQC208-7 devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing.
■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
■ Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
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