Manufacturer | INTEL/ALTERA |
Memory Size | 64kB |
Mounting Type | Surface Mount |
Package / Case | 32-TQFP |
Product Status | Active |
Voltage - Supply | 3V ~ 3.6V |
Programmable Type | OTP |
Operating Temperature | 0°C ~ 70°C (TA) |
Supplier Device Package | 32-TQFP (7x7) |
The MAX 9000 family EPC1064VTC32 of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
The Altera Single Resistors series EPC1064VTC32 is Configuration Devices for SRAM-Based LUT Devices Data Sheet; 12/30/2006; Call Factory, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on
third-generation Multiple Array MatriX (MAX) architecture
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz
■ Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and registered logic
■ FastTrack Interconnect for fast, predictable interconnect delays
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable output slew-rate control to reduce switching noise
■ MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices
■ Configurable expander product-term distribution allowing up to 32 product terms per macrocell
■ Programmable power-saving mode for more than 50% power reduction in each macrocell
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