Manufacturer | Rochester Electronics, LLC |
Speed | - |
Mounting Type | - |
Package / Case | - |
Product Status | Active |
Voltage - Input | - |
Programmable Type | - |
Number of Macrocells | - |
Supplier Device Package | - |
The Altera EP1810LI-45 offers a solution to high-speed, lowpower logic integration. EP1810LI-45 devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array.
The Altera CPLDs series EP1810LI-45 is CPLD Classic Family 900 Gates 48 Macro Cells 22.2MHz 5V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.■ Complete device family with logic densities of 300 to 900 usable gates
■ Device erasure and reprogramming with non-volatile EPROM configuration elements
■ Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz
■ 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages
■ Programmable security bit for protection of proprietary designs
■ 100% generically tested to provide 100% programming yield
■ Programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls
■ Software design support featuring the Altera MAX+PLUS II development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems
■ Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors
■ Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest