The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.

The QL2009 contains 672 logic cells. With 225 maximum I/Os, the QL2009 is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages.

Software support for the complete pASIC families, including the QL2009, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The QuickToolsTM and QuickChipTM packages provide a solution for designers who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation.