Introduction
CD4007 is a dual complementary pair plus inverter. This page will introduce details about the CD4007 inverter, including its pin, features, applications, datasheet, etc.
Current Mirror Circuit using CD4007 in a Laboratory Setting
Catalog
The CD4007M/CD4007C consists of three complementary pairs of N- and P-channel enhancement mode MOS transistors suitable for series/shunt applications. The IC works in a variety of environments and connects directly to CMOS, NMOS, and TTL devices. The IC provides a wide range of applications, including strong noise immunity and low thermal dissipation. All pin voltages must be restricted to remain between VSS and VDD at 0.3V at all times in order for the device to function properly. Clamping diodes are used at VD and VSS to provide static protection for all inputs.
An inverter configuration inverts the input digital signal. An inverter always has high or logic level 1 output when its input is low or at logic level 0, and a low or logic level 0 output when the input is high or at logic level 1.
Figure1-CD4007 Pinout
Pin No |
Pin Name |
Description |
1 |
2Dp |
The drain of p Channel 2 |
2 |
2Sp |
Source of p Channel 2 |
3 |
2A |
Input Channel 2 |
4 |
2sn |
Source of n Channel 2 |
5 |
2Dn |
Drain of n Channel 2 |
6 |
1A |
Input Channel 1 |
7 |
VSS |
Source Supply |
8 |
1Dn |
Drain of n Channel 1 |
9 |
3Sn |
Source of n Channel 3 |
10 |
3A |
Input Channel 3 |
11 |
3Sp |
Source of p Channel 3 |
12 |
3Y |
output |
13 |
1Dp |
Drain of p Channel 1 |
14 |
VDD |
Drain Supply |
- tPHL, tPLH = 30 ns (typ) at 10V
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Devices”
age-Temperature Range; 100nA at 18V and +25oC
Figure2-CD4007 Connection Diagram
Figure3-schematic and pinout for the CD4007
Three individual inverters can be constructed from one CD4007 package.
Firstly, Connecting pins 8 and 13 together as the inverter output is the simplest configuration. The pin will be the input. Please confirm to connect pin 14VDD to power and pin 7 VSS to ground.
Figure4-CD4007 Inverter
Pins 2 and 4 are linked to VDD and VSS, respectively, pins 1 and 5 are connected as the output, and pin 3 is connected as the input to create the second inverter. Connecting pins 11 to VDD, 9 to VSS, 12 to be the output, and 10 to be the input creates the third inverter.
Part Number |
|||
Manufacturer |
|||
Package / Case |
14-SOIC (0.154, 3.90mm Width) |
14-SOIC (0.154, 3.90mm Width)14-SOIC (0.154, 3.90mm Width) |
|
Number of Pins |
14 |
14 |
14 |
Logic Function |
Inverter |
|
Inverter |
Number of Circuits |
2 |
|
|
Number of Output Lines |
3 |
|
|
Propagation Delay |
50ns |
18ns |
55 ns |
Min Supply Voltage |
3 V |
|
3 V |
Supply Voltage |
3V ~ 15V |
5 V |
3V ~ 18V |
Figure5-CD4007 Dimensions
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