Manufacturer | Intel |
Mounting Type | Surface Mount |
Number of I/O | 153 |
Package / Case | 208-BFQFP Exposed Pad |
Product Status | Obsolete |
Number of Gates | 12000 |
Programmable Type | In System Programmable |
Number of Macrocells | 560 |
Delay Time tpd(1) Max | 20 ns |
Operating Temperature | -40°C ~ 85°C (TA) |
Supplier Device Package | 208-RQFP (28x28) |
Voltage Supply - Internal | 4.5V ~ 5.5V |
Number of Logic Elements/Blocks | 35 |
General Description
The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for MAX 9000 devices.
Features
■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz
■ Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and registered logic
■ FastTrack® Interconnect for fast, predictable interconnect delays
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable output slew-rate control to reduce switching noise
■ MultiVolt™ I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices
■ Configurable expander product-term distribution allowing up to 32 product terms per macrocell
■ Programmable power-saving mode for more than 50% power reduction in each macrocell
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable security bit for protection of proprietary designs
■ Software design support and automatic place-and-route provided by Altera’s MAX+PLUS® II development system on Windows based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■ Programming support with Altera’s Master Programming Unit (MPU), BitBlasterTM serial download cable, ByteBlasterT parallel port download cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third-party manufacturers
■ Offered in a variety of package options with 84 to 356 pins (see Table 2
■ Low-cost, high-density, register-rich CMOS programmable logic
device (PLD) family (see Table 1)
– 2,500 to 16,000 usable gates
– 282 to 1,500 registers
■ System-level features
– In-circuit reconfigurability (ICR) via external configuration
devices or intelligent controller
– Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 5.0-V operation
– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
– MultiVoltTM I/O interface enabling device core to run at 5.0 V,
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
– Low power consumption (typical specification is 0.5 mA or less in
standby mode)
■ Flexible interconnect
– FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed, high-fan-in
logic functions (automatically used by software tools and
megafunctions)
– Tri-state emulation that implements internal tri-state nets
■ Powerful I/O pins
■ Programmable output slew-rate control reduces switching noise
Intel Corporation, commonly known as Intel, is an American multinational technology company that specializes in the design and manufacturing of semiconductor chips and related technologies for a wide range of computing and communication devices. Intel enables designers of electronic systems to rapidly and cost effectively innovate, differentiate, and win in their markets. Intel offers FPGAs, SoCs, CPLDs, and Power Solutions, to provide high-value solutions to customers worldwide.It is one of the world's largest and most influential semiconductor chip manufacturers.
Intel's microprocessors have played a pivotal role in the development of personal computers (PCs) and other computing devices. The Intel 4004, introduced in 1971, was the world's first commercially available microprocessor. Since then, Intel has continued to innovate and release a series of successful microprocessor families, such as the Intel 8008, Intel 8086, Intel Pentium, Intel Core, and more.